Analog and Mixed Signal Layout Engineer

Overview

Analog and mixed-signal layout engineer developing high-speed connectivity IPs for AI, networking and next-generation compute systems, using advanced semiconductor process technologies.

What you'll do

• Design and implement complex analog, mixed-signal and RF layouts for high-performance connectivity IPs, including floorplanning, device placement and routing.
• Work closely with circuit designers to translate schematics into robust physical implementations from floorplanning through tapeout.
• Own physical verification and signoff closure including DRC, LVS, ERC, antenna, DFM and EMIR.
• Optimize layouts using extraction results to meet performance, matching, noise and reliability targets.
• Contribute to layout reviews and help drive effective layout methodologies and best practices.
• Improve layout productivity and quality through automation, scripting and AI-assisted workflows.

What you'll need

• BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field, with 5–10 years of experience in analog, mixed-signal, RF or custom layout development.
• Hands-on experience with layouts for SerDes, data converters, clocking circuits, power management, transceiver building blocks or related connectivity IPs.
• Proven experience in full-custom layout and signoff including RC extraction, DRC, LVS, ERC, DFM and EMIR.
• Experience with advanced semiconductor technologies including CMOS, FinFET, BiCMOS or SiGe.
• Strong understanding of semiconductor process technologies, device physics and layout-dependent effects.
• Proficiency with Cadence Virtuoso and industry-standard EDA tools.
• Experience leveraging automation, scripting or AI-assisted methodologies to improve layout productivity and quality.
• Solid understanding of layout techniques including matching, shielding, clock distribution, power planning, ESD protection, latch-up prevention, manufacturability and reliability-aware design.
• Demonstrated success delivering complex layouts through tapeout.
• Ability to work effectively with globally distributed design, verification, CAD and technology teams.
• Experience supporting multiple projects in a fast-paced product development environment.

Nice to have

• Exposure to silicon photonics, co-packaged optics (CPO), near-package optics (NPO), optical transceivers or high-bandwidth connectivity solutions.

Details

• Location: Bengaluru, India.