Senior Engineer, CAD Physical Verification

Overview

Senior CAD Engineer supporting physical layout, verification, and CMOS integrated circuit design workflows. The role focuses on improving EDA tools and flows, production support, and AI-assisted automation for memory layout teams.

What you'll do

• Support memory layout teams by solving daily challenges and developing lasting solutions.
• Identify improvement opportunities and develop automation solutions.
• Develop reliable layout methodologies to improve time to market.
• Lead AI-assisted and automated placement, routing, and optimization flows.
• Evaluate and implement tools and technologies for layout development.
• Mentor junior team members.
• Develop AI-enabled methodologies for semi-automated floorplanning and parasitic estimation.

What you'll need

• 5+ years of experience in layout automation, physical verification, or related domains.
• Experience customizing design environments and automation utilities for memory layout productivity.
• Experience with custom memory place-and-route flows using tools such as Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, or Itools.
• Working knowledge of Linux.
• Programming fundamentals and exposure to Skill, Perl, Python, and Tcl.
• Knowledge of CMOS manufacturing, layout rules, EMIR, RC extraction, ESD, and latch-up.
• Bachelor’s or master’s degree in Electronics, Electrical, or Computer Engineering.

Nice to have

• Experience with Totem, VoltusXFA, or XA PDN analysis tools.
• Experience debugging DRC, ERC, LVS, DFM, antenna, Calibre, or ICV rule-deck issues.
• Expertise in AI-driven automation for complex layout workflows.

Details

• Location: Hyderabad, Telangana, India.