Silicon Domain Architect

Overview

Develop and maintain SystemC/TLM-based performance models for AI silicon subsystems, driving architecture exploration, validation, performance characterization and stakeholder engagement for next-generation AI silicon products.

What you'll do

• Develop, maintain and enhance SystemC/TLM-based performance models of critical AI silicon subsystems.
• Model SoC fabrics and on-chip communication networks, memory controllers and memory subsystem behavior.
• Model scale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray or pod.
• Model scale-out controllers and fabrics enabling communication across nodes, racks and larger AI clusters.
• Model host CPU to accelerator memory paths, local, host and remote memory access paths, and end-to-end data movement architectures.
• Implement new architectural features based on evolving product requirements, and improve model fidelity, scalability, maintainability and simulation performance.
• Perform debugging and root-cause analysis of model issues and performance anomalies.
• Define and execute validation strategies, plans, regression suites, coverage methodologies and quality metrics for performance models.
• Correlate modeled behavior against architectural expectations, reference simulations, performance projections and available hardware measurements, and resolve discrepancies.
• Design and execute performance studies across a wide range of workloads, traffic patterns and system configurations.
• Analyze bandwidth utilization, latency, congestion, traffic distribution, buffering efficiency and resource utilization of communication fabrics, memory systems and data movement paths.
• Assess scalability of scale-up and scale-out architectures and identify performance bottlenecks with their impact on throughput and efficiency.
• Conduct architectural tradeoff studies and provide performance-driven recommendations to influence architecture and product decisions.
• Develop frameworks, automated workflows, dashboards and visualization tools for large-scale performance data generation, analysis and reporting using Python.
• Partner with architecture, performance stimulus generation, silicon design and product stakeholders; review architectural proposals and present findings to engineering leadership.
• Drive improvements in modeling methodologies, simulation efficiency and automation, and contribute to mentoring and knowledge sharing across the team.

What you'll need

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science or Electronics Engineering.
• 15+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering or related domains.
• Strong software development experience in C++.
• Working proficiency in Python for automation, performance analysis, data processing and visualization.
• Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
• Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products or complex hardware systems.
• Strong understanding of SoC architecture, memory subsystem architecture, memory controllers, cache hierarchies and data movement architectures.
• Strong understanding of on-chip communication fabrics and NoC concepts, high-speed interconnects, and scale-up and scale-out communication architectures.
• Strong understanding of performance bottleneck analysis and latency and bandwidth characterization.
• Experience performing architectural tradeoff analysis and performance characterization studies.
• Experience working with large performance datasets and deriving meaningful engineering insights.
• Strong debugging and root-cause analysis capabilities, and ability to identify bottlenecks and drive optimization recommendations.
• Experience developing validation strategies and performance evaluation methodologies.
• Strong quantitative reasoning and data-driven decision-making skills, and ability to solve complex technical problems independently.
• Strong verbal and written communication skills, ability to collaborate across globally distributed engineering organizations, and strong technical presentation and stakeholder management skills.

Nice to have

• Deep understanding of AI accelerator architectures and modern AI infrastructure.
• Experience modeling memory, communication, interconnect or scalability-related subsystems.
• Experience with Network-on-Chip (NoC) architectures and interconnect performance analysis.
• Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
• Familiarity with AI/ML workloads, large language models, distributed training and inference environments.
• Experience with performance stimulus generation methodologies and workload characterization.
• Experience building automated dashboards and reporting using Power BI, Tableau, Grafana, Plotly or similar technologies.
• Experience evaluating large-scale distributed AI systems and accelerator clusters.
• Experience mentoring engineers and providing technical leadership in cross-functional environments.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site work at the assigned Intel site and off-site.
• Job type: Experienced Hire. Shift: Shift 1 (India).