STAFF ENGINEER, DDEG Design Methodology

Overview

Staff Engineer for DDEG Design Methodology, owning verification and end-to-end analysis of full chip, gate-level custom designs for DRAM design verification.

What you'll do

• Leverage AI-based tools, agentic workflows, and automation to accelerate verification cycle time.
• Develop and maintain test benches and test vectors, and run regressions for coverage analysis.
• Simulate, analyze, and debug pre-silicon block and full-chip designs to improve debug efficiency.
• Create test cases/stimulus to increase functional coverage across DRAM and emerging memory architectures.
• Validate AI outputs against assumptions, specs/standards, simulations, waveforms, assertions, and coverage reports.
• Co-develop verification flows and environments with international colleagues.

What you'll need

• Experience with SystemVerilog and PLI coding.
• UVM testbench experience.
• Knowledge of digital/mixed signal circuits and digital/mixed signal verification.
• Proficiency with SPICE and/or Verilog simulations.
• Hands-on skills writing Verilog and real number models (real number models is stated as a plus).
• Hands-on SV testbench building at block and full-chip level.
• Experience with tools such as Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice.

Nice to have

• Good scripting skills using Perl and/or Python.
• Previous work experience in DRAM memory-related fields.

Details

• Location: Hyderabad, Telangana, India.