Staff Engineer

Overview

Senior modeling engineer role within Broadcom's Central Engineering Group, focused on authoring, debugging and optimizing memory IP EDA models (SRAM, RF, CAM, ROM, etc.) used in ASIC design flows, leading memory modeling and compiler development projects.

What you'll do

• Lead memory modeling and compiler development projects in a technically complex, dynamic schedule environment.
• Write model templates for integration into memory compilers to generate models used in DFT/CAD tools in ASIC development flows.
• Participate in forums for model development, improvement and reviews, and serve as a knowledge resource for peers and subordinates.
• Document work well, prioritize tasks and handle the multiple facets of model development projects independently.
• Improve memory models and model generation flows for better performance, user experience and quality.
• Work directly with IP design teams, compiler teams and tool vendors globally to resolve model-related issues.
• Respond to library support requests and address tickets on model issues from product teams across Broadcom.

What you'll need

• BS degree in EE/CS/CE with programming/coding experience and 8+ years of industry experience, or MS degree with 6+ years of industry experience, or Ph.D. in EE/CS with 3+ years of industry experience.
• At least 3 years of experience using Linux systems, with excellent knowledge of Linux commands, file systems, and job execution.
• Verilog modeling skills (strong preference for 5+ years).
• Static and dynamic timing analysis knowledge.
• Experience with chip design tools and flows: DFT (Tessent, LogicVision, Modus; at-speed scan test, Logic BIST, Memory BIST), synthesis (Design Compiler, Genus), simulation (VCS, Questa, Verilog, waveform viewers, simulation debug).
• UVM verification testbench and methodology development.
• Familiarity with Verilog/RTL/Behavioral/Timing/Power/DFT/ATPG/synthesizable model development for SRAMs, RF, CAM, ROM and other memories.
• Experience writing directed testbenches in Verilog for model verification.
• Knowledge and experience using simulators: NC, VCS, ModelSim, ESPCV (must have).
• Familiarity with memory model verification/QC flow (required).
• Scripting and flow automation skills in Perl, Python, Tcl and Shell programming (required).
• Ability to work in agile and dynamic development environments.
• Excellent written and verbal communication skills.
• Skilled multi-tasking and context-switching abilities (must have).
• Strong analytical, problem-solving and quick-learning skills.
• Team player, methodical, detail-oriented, independent, well organized, and able to remain calm under high pressure.

Details

• Location: Bangalore Electronic City, India.