Staff Engineer

Overview

Staff-level design verification role focused on hands-on SystemVerilog/UVM development for high-performance CPU verification, with emphasis on RISC-V.

What you'll do

• Perform hands-on SystemVerilog/UVM development for modern high-performance CPU verification.
• Write test cases and use test generators to create targeted tests for RISC-V CPU verification.
• Work with internal test generators to target coverage and test-plan scenarios.

What you'll need

• 7-12 years of experience in DV, preferably in CPU verification.
• Bachelor's or master's degree.
• Proficiency in SystemVerilog and UVM methodology.
• Very good object-oriented programming skills.
• Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing and test plan implementation experience.

Nice to have

• Any scripting knowledge, preferably Python.
• Bus interface knowledge such as AXI or PCIe.
• Integration experience with third-party VIPs, such as bus VIPs.
• CPU micro-architecture knowledge.

Details

• Location: Bengaluru, Karnataka, India.
• Requires a successful background and reference check and proof of right to work in India.
• Offer is contingent on authorization for access to export-controlled technology under applicable export control laws, or the ability to obtain any necessary export license or approvals.