Staff Engineer, Design Verification Engineering

Overview

Staff Design Verification Engineer providing technical leadership in developing verification strategies for complex analog and mixed-signal designs, architecting verification environments, mentoring junior engineers, and collaborating across organizational boundaries.

What you'll do

• Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments.
• Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality.
• Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors.
• Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria.
• Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis.
• Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy.
• Lead post-silicon validation activities, contributing expertise to address critical issues.
• Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment.

What you'll need

• Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs.
• Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure.
• Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches.
• Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction.
• Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques.
• Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks.
• Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams.
• 7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification (preferred in source; see Nice to have).

Nice to have

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification.

Details

• Location: Bangalore, RMZ, India.
• Required travel: Yes, 10% of the time.
• Shift type: 1st Shift/Days.
• Job requisition type: Experienced.
• Applicants other than US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) may have to go through an export licensing review process for positions requiring access to technical data.