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Vhdl Questions Set 10:

Quiz Mode

The driver of signal `y` is:

x and z

Solution:

Which of the following data types is a subtype of INTEGER?

NATURAL

REAL

CHARACTER

STD_LOGIC

Solution:

Which of the following is a characteristic of Verilog HDL?

Strongly typed language

Better library

Not portable

Case-sensitive

Solution:

Which part of a VHDL code provides the complete description of the desired circuit?

Library

Configurations

Entity

Architecture

Solution:

Which of the following is not defined by the entity?

Direction of any signal

Names of signal

Different ports

Behavior of the signals

Solution:

Which of the following options is completely legal, given that `a` and `b` are two UNSIGNED type signals?

x <= a + b; y <= a - b;

x <= a OR b; y <= a AND b;

x <= a + b; y <= a OR b;

x <= a OR b; y <= a + b;

Solution:

Which of the following is a disadvantage of using Verilog?

Weakly-typed language

Flexible modelling capabilities

Description can include the very abstract to the very structural

Can express large, complex designs (>10^7 gates)

Solution:

Look at the following array declarations:

`TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array2 IS ARRAY ( 0 TO 3 ) OF array1;`

How many total bits can be stored in these arrays?

16 bits

80 bits

64 bits

128 bits

Solution:

Which of the following is the correct way to leave a port unconnected in VHDL?

L1 : my_component PORT MAP(a); a <= OPEN;

L1 : my_component PORT MAP(a := OPEN);

L1: my_component PORT MAP(a => OPEN);

L1 : my_component PORT MAP(a); a := OPEN;

Solution:

A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of the EXIT statement, the control will be passed ________

Outside the FOR loop

Outside the WHILE loop

At the next iteration of the WHILE loop

At the next iteration of the FOR loop

Vhdl Questions Set 10:

The driver of signal `y` is:

Solution:

Which of the following data types is a subtype of INTEGER?

Solution:

Which of the following is a characteristic of Verilog HDL?

Solution:

Which part of a VHDL code provides the complete description of the desired circuit?

Solution:

Which of the following is not defined by the entity?

Solution:

Which of the following options is completely legal, given that `a` and `b` are two UNSIGNED type signals?

Solution:

Which of the following is a disadvantage of using Verilog?

Solution:

Look at the following array declarations:

`TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array2 IS ARRAY ( 0 TO 3 ) OF array1;`

How many total bits can be stored in these arrays?

Solution:

Which of the following is the correct way to leave a port unconnected in VHDL?

Solution:

A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of the EXIT statement, the control will be passed ________

Solution:

Related Question Sets:

Related Topics:

Vhdl Questions Set 10:

The driver of signal y is:

Solution:

Which of the following data types is a subtype of INTEGER?

Solution:

Which of the following is a characteristic of Verilog HDL?

Solution:

Which part of a VHDL code provides the complete description of the desired circuit?

Solution:

Which of the following is not defined by the entity?

Solution:

Which of the following options is completely legal, given that a and b are two UNSIGNED type signals?

Solution:

Which of the following is a disadvantage of using Verilog?

Solution:

Look at the following array declarations: TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array2 IS ARRAY ( 0 TO 3 ) OF array1; How many total bits can be stored in these arrays?

Solution:

Which of the following is the correct way to leave a port unconnected in VHDL?

Solution:

A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of the EXIT statement, the control will be passed ________

Solution:

Related Question Sets:

Related Topics:

The driver of signal `y` is:

Which of the following options is completely legal, given that `a` and `b` are two UNSIGNED type signals?

Look at the following array declarations:

`TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array2 IS ARRAY ( 0 TO 3 ) OF array1;`

How many total bits can be stored in these arrays?