CPU Design Verification Sr Lead Engineer

Overview

Qualcomm is hiring DV engineers to verify high performance and low power CPUs in Bangalore / Hyderabad.

What you'll do

• Responsible for power management verification, including Boot, Reset, clock gating, power gating, voltage/frequency management, limit management and throttling.
• Work closely with design/verification teams within CPU to develop comprehensive test plans.
• Use simulation and formal verification methodologies to execute test plans; write checkers, assertions and develop stimulus.
• Verify power intent through methodologies such as UPF.
• Work closely with system architects, software teams and SoC team to validate system use cases.
• Work closely with the emulation team to enable verification on emulators and FPGA platforms.
• Debug and triage failures in simulation, emulation and/or silicon.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• BE/BTech degree in CS/EE with 4+ years' experience.
• Experience in power management verification.
• Implementation of assembly and C language embedded firmware.
• Experience in C/C++, scripting languages, Verilog/SystemVerilog.
• Strong understanding of power management features in CPUs and CPU based SoCs.
• Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Nice to have

• Good understanding of CPU architectures and CPU micro-architectures.
• In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
• Experience with advanced verification techniques such as formal and assertions is a plus.
• Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus.

Details

• Location: Bangalore / Hyderabad, India.