CPU Power Modeling & Characterization Engineer, Staff

Overview

Work as a CPU Power Modeling Engineer on high-performance, low-power CPU clusters (CPUSS / NCC) across pre-silicon and post-silicon phases. Focus on DPM/EMON-based power modeling, event-to-energy correlation, and power-performance tradeoff analysis.

What you'll do

• Develop CPU power models based on architectural micro-events, PMU/EMON counters, and DPM frameworks.
• Build unconstrained vs HW-limited CPU power models incorporating Limiters, DVFS, temperature, and throttling behavior.
• Model dynamic power, leakage, and rail-specific behavior.
• Drive DPM weight characterization using simulation, emulation, and silicon data across representative workloads.
• Correlate CPU event counts with measured silicon power and debug gaps.
• Enhance DPM coverage by adding new CPU events and diags.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• Minimum 7 years of experience.
• Strong understanding of CPU micro-architecture.
• Hands-on experience with DPM / EMON / PMU-based power modeling.
• Experience with pre-silicon and post-silicon power correlation.
• Proficiency in Python/Perl and data analysis.

Details

• Location: Bangalore, India.