DDR Design Verification Lead Engineer

Overview

Qualcomm is hiring a DDR Design Verification Lead Engineer to verify LPDDR/DDR based IPs and subsystems in the Infra IP team.

What you'll do

• Create DV infrastructure for verification.
• Integrate VIPs.
• Create and execute test plans, debug failures, write assertions, and close code and functional coverage.
• Ensure high quality verification.
• Work with all stakeholders to ensure program success.

What you'll need

• Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.
• 11+ years Hardware Engineering experience or related work experience.
• Strong debug, UVM and SystemVerilog skills.
• Understanding of specs and standards, and developing relevant test plans.
• Monitors, scoreboards, sequencers and sequences, using scripts, SystemVerilog, UVM and methodologies to increase the rate at which bugs are found and resolved.
• Comfortable checking builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug.
• Willingness to dig into fails and understand what is happening.

Nice to have

• 4+ years of industry experience in: thorough understanding of digital design concepts; thorough understanding of DV methodologies and tools; good understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5); understanding of bus protocols like AHB/AXI/ACE/ACE-Lite.

Details

• Location: Hyderabad, Telangana, India.