Staff Engineer - ASIC DV

Overview

Staff Engineer on the ASIC Design Verification team, responsible for verification of IP/Block or Subsystem, from test plan creation and SystemVerilog/UVM testbench development through to sign-off.

What you'll do

• Be responsible for overall IP/Block and Subsystem verification, from test plan creation, SystemVerilog/UVM testbench development to sign-off.
• Lead and mentor a team of verification engineers.
• Ensure first pass product through verification coverage and sign-off criteria.
• Pair with similar domain specialists across other geographical locations on core technical initiatives.

What you'll need

• M.S./M.Tech or BS/BE in Electronics, with 10+ years of experience.
• Expertise in IP/Block/Subsystem level verification.
• Experience with AMBA protocols such as AXI/AHB.
• PCIe/NVMe/DDR protocol knowledge and work experience on DDR/PCIe/NVMe controllers or similar IPs.
• Proven track record of building Verification Plans, UVM Environments and Test Benches.
• Experience with RTL debugging, Scoreboards, Assertions, Functional coverage coding and Code Coverage analysis.
• Sound knowledge of Verilog and SystemVerilog languages.
• Good written and verbal communication skills, with a strong commitment and ability to work in cross-functional and global teams.

Nice to have

• NVMe protocol knowledge and experience working on NVMe controllers.
• Good exposure and familiarity with security-related aspects (boot, ROM, FW protection, key generation, etc.).
• Experience using AI tools (such as Claude).
• Prior experience managing a team of at least 5 DV engineers.
• Experience technically leading an IP/Block to completion.

Details

• Domain: IP/Block/Subsystem Verification (RTL Front end verification).
• Location: Bengaluru, Karnataka, India.