Staff Engineer - ASIC DV

Overview

Staff-level ASIC Design Verification role responsible for verifying IP, blocks or subsystems, from test plan creation through System Verilog/UVM testbench development to sign-off, with the ability to lead and mentor a verification team.

What you'll do

• Be part of a highly skilled ASIC team working on the latest technologies.
• Be responsible for overall IP/Block and Subsystem verification, from test plan creation and System Verilog/UVM testbench development to sign-off.
• Lead and mentor a team of verification engineers.
• Ensure first pass product through verification coverage and sign-off criteria.
• Pair with similar domain specialists across other geographical locations on core technical initiatives.

What you'll need

• M.S./M.Tech or BS/BE in Electronics, with 10+ years of experience.
• Expertise in IP/Block/Subsystem level verification.
• Experience with AMBA protocols such as AXI/AHB.
• PCIe/NVMe/DDR protocol knowledge and work experience on DDR/PCIe/NVMe controllers or similar IPs.
• Proven track record of building Verification Plans, UVM environments and testbenches.
• Experience with RTL debugging, scoreboards, assertions, functional coverage coding and code coverage analysis.
• Sound knowledge of Verilog and System Verilog.
• Good written and verbal communication skills, and a strong commitment to working in cross-functional and global teams.

Nice to have

• NVMe protocol knowledge and experience working on NVMe controllers.
• Good exposure and familiarity with security-related aspects (boot, ROM, FW protection, key generation, etc.).
• Experience using AI tools (Claude etc.).
• Prior experience managing a team of at least 5 DV engineers.
• Experience technically leading an IP/Block to completion.

Details

• Domain: IP/Block/Subsystem Verification (RTL front-end verification).
• Location: Bengaluru, India.