Staff Engineer- AMS Verification

Overview

Staff Engineer responsible for AMS verification of advanced mixed-signal and SoC designs, using SystemVerilog real-number modelling and mixed-signal simulation environments to support pre-silicon validation.

What you'll do

• Play a key role in the development and implementation of advanced System Verilog real-number modelling methodologies for analog/mixed-signal (AMS) verification, optimizing speed and accuracy trade-offs for pre-silicon validation.
• Collaborate with design and verification teams to define and refine functional verification plans for AMS blocks, ensuring proper integration into complex System-on-Chip (SoC) architectures.
• Develop and maintain custom verification frameworks that incorporate mixed-signal and digital simulation environments using industry-leading tools such as Xcelium and VCS.
• Create, validate, and deploy behavioral models using Verilog-AMS and SystemVerilog for AMS components, ensuring compatibility with the digital verification environment and system-level requirements.
• Identify bottlenecks in current AMS verification flows and propose innovative solutions to enhance efficiency, scalability, and coverage.
• Provide technical mentorship and training to junior engineers, fostering expertise in AMS verification techniques and best practices.

What you'll need

• Strong debugging and problem-solving skills, capable of driving verification excellence for advanced mixed-signal and SoC designs while working effectively in cross-functional global teams.
• Proven experience in AMS verification for complex SoCs and subsystem-level designs.
• Strong proficiency in mixed-signal simulation environments using Cadence, Synopsys, or Mentor Graphics tool suites.
• Solid understanding of digital design methodologies, Verilog HDL, RTL design practices, and analog circuit fundamentals.
• Hands-on experience with behavioral modeling, including Verilog-D, Verilog-A, and Verilog-AMS.
• Strong functional knowledge of analog and mixed-signal building blocks, including comparators, op-amps, switched-capacitor circuits, ADCs, DACs, current mirrors, charge pumps, regulators, and clocking circuits.
• Understanding of power management architectures, data converters, and analog functional specifications.
• Working knowledge of scripting languages such as Python, Perl, Tcl, SKILL, or equivalent automation tools.
• Demonstrated ability to lead technical projects, collaborate across global teams, and thrive in a multi-site development environment.
• Experience with industry-standard AMS verification tools, including Cadence Xcelium + Spectre, Synopsys XA-VCS, and Mentor Eldo ADMS.

Nice to have

• Prior analog design experience.
• Exposure to SystemVerilog (SV) and UVM testbench development and enhancement from a mixed-signal verification perspective.
• Loop analysis knowledge.

Details

• Location: Bangalore, India.