Design Methodology – Staff DRAM Power Integrity Engineer

Overview

Staff DRAM Power Integrity Engineer in the Design Methodology group, developing and standardizing EM/IR methodology across all DRAM products.

What you'll do

• Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes.
• Perform static and dynamic EM/IR analysis using RedHawk or Totem or other industry-standard tools; identify root-cause issues such as high-resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams.
• Actively leverage AI-based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis.
• Maintain a strong understanding of the full EMIR flow, from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation, and ensure accurate evaluation across operating modes and temperatures.
• Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst-case vectors, and standardize analysis expectations across global teams.
• Collaborate with cross-geographical teams and EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams.
• Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs.

What you'll need

• Master's degree in electrical or computer engineering.
• 4 - 8 years of experience in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.
• Deep hands-on experience with Ansys RedHawk or Totem for full-chip EM/IR verification and PDN analysis, including setup, scenario creation, debug, and root-cause analysis.
• Expertise in vectorless and dynamic/pattern-based IR-drop analysis, with strong ability to interpret current behavior, switching activity, and voltage-sensitivity trends.
• Proven ability to identify root causes of IR-drop issues, including switching activity, grid resistance, parasitics, routing topology, and translate analysis results into actionable design or layout fixes.
• Experience performing SoC-level or chip-level EMIR signoff and supporting tapeouts.
• Solid understanding of PDN interactions with circuit timing/margin, layout topology, and chip-level power architecture.
• Ability to understand the full end-to-end design flow, including RTL, floorplanning, routing, extraction, EMIR, STA, and silicon correlation.
• Familiarity with Make or similar automation frameworks for EMIR rollups.
• Hands-on experience with low-power, multi-voltage, power-off, or mixed-signal designs.
• Experience in chip-level IR/EM analysis and driving closure across multi-functional teams.

Nice to have

• Experience with power-modeling or current-source modeling flows (e.g., CPM).
• Scripting skills in Python/Tcl for automation and data analysis.
• Experience in improving EMIR/PI analysis flows or methodology.
• Knowledge of PnR or STA tools (FusionCompiler, PrimeTime).
• Background in circuit design with SPICE experience.
• Exposure to or strong interest in AI/ML-assisted design flows, agentic AI or advanced automation in circuit design and verification.
• Familiarity with memory-product power behavior (DRAM/SRAM/NAND).

Details

• Location: Hyderabad - Phoenix Aquila, India.