DFT Senior Engineer

Overview

Senior DFT engineer working across SoC design-for-test activities for Broadcom APD's ASIC designs, including DFT architecture, test insertion and verification, pattern generation, coverage improvement and post-silicon debug.

What you'll do

• Work on various phases of SoC DFT activities for Broadcom APD (ASIC Product Division) designs: DFT architecture, test insertion and verification, pattern generation, coverage improvement, post-silicon debug and yield improvement to meet product test metrics.
• Work with the Physical Design and STA team for DFT mode timing closure.
• Interact directly with external customers, as the role could involve this.
• Work with teams across multiple geographies.
• Handle work independently.

What you'll need

• In-depth knowledge of DFT concepts.
• Experience in DFT aspects including ATPG, MBIST and IJTAG.
• Experience with DFT insertion and verification, pattern generation, coverage improvement, vector simulation and post-silicon debug.
• Strong problem solving and debugging skills.
• Excellent communication skills.
• Bachelor's degree with 5+ years of relevant experience, or Master's degree with 3+ years of relevant experience.

Nice to have

• Expertise in scripting languages such as Perl, shell, etc.
• Experience with Mentor Graphics DFT tools (Tessent Shell) is highly desirable.

Details

• Location: Pune, India (EON Kharadi Infrastructure).