DFT - Senior Engineer

Overview

As an ASIC engineer on the Engineering Group ASICS team, you will define, model, design, optimize, verify, validate, implement and document IP (block/SoC) development for high performance, low power products, collaborating with cross-functional groups to determine the product execution path.

What you'll need

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field.
• Minimum of 3+ years of experience in the area of ASIC/DFT.
• In-depth knowledge of DFT concepts.
• In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
• Expertise in test mode timing constraints definition, and knowledge of providing timing fixes/corrective actions for timing violations.
• Expertise in scripting languages such as Perl, shell, etc.
• Experience in simulating test vectors.
• Knowledge of equivalence check, and DFT DRC rules both in RTL lint tools (like Spyglass) and ATPG tools (like Tessent, TK, TetraMax).
• Ability to work in an international team and dynamic environment.
• Ability to learn and adapt to new tools and methodologies.
• Ability to multi-task and work on several high priority designs in parallel.
• Excellent problem solving skills.
• Excellent communication and teamwork skills, and good English.

Nice to have

• Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test.

Details

• Location: Bangalore, India.