Director, Silicon Logical Design

Overview

Lead the design and development of complex, high-performance SoCs for next-generation AI acceleration platforms, combining technical leadership with people leadership and engineering execution.

What you'll do

• Provide technical leadership for microarchitecture, RTL design and SoC integration, driving design decisions and trade-offs across functionality, performance, power and area.
• Lead engineering execution and delivery of complex SoC designs, ensuring alignment with project milestones, quality objectives and tapeout schedules.
• Drive design quality and implementation readiness, including CDC/RDC, synthesis, timing closure and physical implementation considerations.
• Collaborate with architecture, verification, DFT and physical design teams to resolve complex technical challenges and ensure successful silicon delivery.
• Identify and manage technical risks, resource requirements and cross-functional dependencies to ensure effective project execution.
• Build, lead and develop a high-performing engineering team through coaching, mentoring, performance management and talent development.
• Drive continuous improvement in design methodologies, engineering processes and team productivity.
• Represent the design team in technical reviews, project planning and cross-functional discussions, ensuring alignment with broader engineering objectives.

What you'll need

• Degree in Electronic Engineering, Computer Science or a related discipline with 18+ years of experience.
• Extensive experience in ASIC/SoC design and development, including technical leadership and engineering management.
• Proven experience leading engineering teams through multiple complex SoC tapeouts, with end-to-end ownership of design execution and delivery.
• Strong expertise in digital design, microarchitecture, RTL development and complex SoC integration.
• In-depth knowledge of Verilog/SystemVerilog, SoC interconnect protocols and clock/reset architectures.
• Good understanding of synthesis, static timing analysis, CDC/RDC, low-power design and physical implementation considerations.
• Demonstrated ability to manage technical risks, schedules, resources and cross-functional dependencies across complex silicon development programs.
• Proven experience in building, managing and developing high-performing engineering teams.
• Strong technical judgement, problem-solving and decision-making skills.
• Excellent communication, stakeholder management and collaboration skills, with experience working across globally distributed teams.

Nice to have

• Experience in high-performance, multicore or AI accelerator SoC development.
• Experience with advanced process technologies and physically aware RTL design.
• Knowledge of DFT methodologies, low-power design and multi-voltage domain integration.
• Experience with multi-die or chiplet-based SoC architectures.
• Knowledge of high-speed interfaces such as PCIe, DDR and Ethernet.
• Experience in silicon bring-up, post-silicon debugging and ECO implementation.
• Experience driving engineering methodology improvements and design automation.

Details

• Location: Bengaluru, India.