Lead Engineer - CAD Physical Verification

Overview

Lead the CAD Physical Verification team within Silicon Labs' central CAD group, supporting design and layout teams through chip development by building, supporting and debugging physical verification rule decks and flows.

What you'll do

• Support design and layout teams to resolve PV-related issues during the design development cycle.
• Develop and QA physical verification rule decks such as DRC, Dummy fill, Antenna and other custom decks.
• Conduct and drive impact analysis meetings with stakeholders for deck updates.
• Collaborate closely with CAD, ESD, Design, Layout, Packaging and foundry teams to obtain requirements for deck development.
• Conduct code reviews and create custom QA testcases to validate the quality of rule decks.
• Develop and maintain PV flows and methodologies to improve quality and performance.
• Perform new tool/feature evaluations and benchmarks.
• Work closely with external vendors to report and track bugs in the software.

What you'll need

• 5+ years of related professional experience.
• Bachelor's or Master's degree in electrical engineering.
• Proficiency in developing and supporting DRC rule decks, including custom rules in Calibre SVRF or similar languages.
• Experience working with design/layout engineers in debugging PV issues.
• Knowledge of physical verification tools such as PVS, Pegasus, Calibre RVE, Calibre DRV and Virtuoso layout editor.
• Proficiency in scripting languages such as PERL, Python or Shell for developing custom scripts.
• Excellent communication skills and experience collaborating with different teams to collect initial specs, develop decks, support them and lead deck impact analysis meetings.
• Ability to work independently, drive decision-making, be detail oriented, and have strong documentation skills.

Nice to have

• Experience in coding LVS, extraction and PERC rule decks.