Staff Engineer IP Verification - Digital Design Verification

Overview

Staff-level engineer leading complete verification ownership of complex block-level custom designs with advanced low power and power management across DDR5, LPDDR5, DDR6 and LPDDR6 memory technologies.

What you'll do

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification.
• Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM).
• Run directed and constrained-random tests and regressions; analyze results and triage failures.
• Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout.
• Provide verification support to design projects by simulating, analyzing, and debugging block level RTL.
• Develop test cases/stimulus to increase the functional coverage for all DRAM architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Debug RTL / testbench / environment issues and partner with design engineers to identify root cause, propose fixes, and prevent recurrence.
• Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure.
• Lead verification efforts for strategic IPs and complex subsystems.
• Influence verification methodology across projects.
• Mentor junior engineers and drive verification quality, productivity, and innovation.
• Provide technical leadership across geographically distributed teams.
• Lead team, guide and set the direction for the verification effort for any project the team undertakes.
• Define roadmap and future scope of verification methodologies.
• Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.

What you'll need

• Good understanding of digital circuits and experience in RTL Verification.
• Understanding of the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium.
• Hands-on experience in building SV, UVM based verification testbenches at block level.
• Good scripting skills using Perl and Python.
• Previous work experience in DRAM memory related fields.
• Good communication and debugging skills and ability to work well in a team.
• Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks.
• Bachelor's with 7-9 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 6-8 years of experience.

Details

• Location: Hyderabad, Telangana, India.