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Senior Engineer IP Verification - Digital Design Verification

Micron Technology
NewPosted today

LOCATION

Hyderabad · Onsite

EXPERIENCE

2+ Years

SKILLS REQUIRED

Digital DesignUVMSystemverilogVerification PlanningRoot Cause AnalysisVerilogPythonPerlDebugging

Job description

Overview

Senior Engineer in IP Verification for digital design, responsible for block and chip RTL verification of DRAM and emerging memory designs.

What you'll do

  • Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification.
  • Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM).
  • Run directed and constrained-random tests and regressions; analyze results and triage failures.
  • Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout.
  • Provide verification support to design projects by simulating, analyzing, and debugging block level RTL.
  • Develop test cases and stimulus to increase functional coverage for all DRAM architectures and features.
  • Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
  • Co-work with international colleagues on developing new verification flows for challenges in DRAM and emerging memory design.
  • Debug RTL, testbench, and environment issues; partner with design engineers to identify root cause, propose fixes, and prevent recurrence.
  • Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure.
  • Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.

What you'll need

  • Good understanding of digital circuits and experience in RTL Verification.
  • Understanding of the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium.
  • Hands-on experience in building SV, UVM based verification testbenches at block level.
  • Good scripting skills using perl, python.
  • Previous work experience in DRAM memory related fields.
  • Good communication and debugging skills and ability to work well in a team.
  • Bachelor's with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience.

Details

  • Location: Hyderabad, Telangana, India.

Read the full description and apply on the company’s own careers page.

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Senior Engineer IP Verification - Digital Design Verification