Senior Principal Engineer, SoC Design Verification

Overview

Senior Principal SoC Design Verification Engineer serving as a senior technical authority for verification of custom System-on-Chip designs, defining strategy for the most complex verification initiatives.

What you'll do

• Define verification strategy, architecture, and signoff criteria for the most complex SoC programs, multiple interdependent technical areas, or a portfolio of related designs.
• Lead high-impact technical initiatives critical to business and functional objectives, including strategy, planning, risk management, and execution alignment across organizations.
• Architect scalable verification platforms, methodologies, reference models, assertions, coverage solutions, and automation strategies for adoption across multiple programs.
• Establish verification readiness and quality frameworks, drive closure of critical risks, and provide evidence-based signoff recommendations to senior engineering and program leadership.
• Solve critical, novel, and nonrecurring problems of exceptional complexity and establish systematic approaches that prevent recurrence across products and teams.
• Lead cross-functional, cross-site, and multi-program resolution of critical issues with architecture, RTL design, firmware, DFT, emulation, physical design, and post-silicon teams.
• Initiate and drive transformative technical innovation and continuous-improvement initiatives with measurable quality, productivity, cost, schedule, or business impact.
• Coach and mentor senior engineers and technical leaders, shape technical direction, and serve as a key technical advisor to functional and program leadership.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

What you'll need

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 8+ years of relevant industry experience; OR Bachelor's degree in a related field with 11+ years of relevant industry experience.
• Demonstrated exceptional mastery and breadth in SoC design verification and recognition as a senior technical authority across multiple programs or technical areas.
• Expert-level experience using SystemVerilog, UVM, constrained-random verification, functional coverage, and SystemVerilog assertions.
• Advanced scripting, automation, and data-analysis experience using Python, Tcl/Tk, Perl, Shell, or equivalent languages.
• Extensive experience with EDA verification, debug, and signoff tools in a UNIX design environment.
• Demonstrated success defining strategy and leading high-impact technical initiatives across complex programs and organizational boundaries.
• Demonstrated ability to solve critical problems of exceptional complexity through innovative, scalable, and sustainable approaches.
• Ability to influence senior cross-functional leadership, communicate complex tradeoffs, and drive alignment on technical direction and investment priorities.
• Demonstrated ability to coach senior engineers and technical leaders and elevate technical capability across teams and programs.

Nice to have

• Experience with power-aware verification using UPF, including isolation, retention, and power-state transitions.
• Experience with a CPU architecture such as RISC-V, Arm, or MIPS.
• Experience with common SoC protocols or interfaces such as AXI, AHB, APB, SPI, I²C, or UART.
• Experience with UVM RAL, SystemRDL, IP-XACT, or register-model generation flows.
• Experience with formal verification, gate-level simulation, emulation, FPGA prototyping, or hardware/software co-verification.
• C or C++ experience related to embedded software, test development, or reference models.

Details

• Location: Hyderabad.