Lead I/O Design Engineer

Overview

Lead the design of custom I/O circuits, including ESD protection, level shifters, input buffers, output drivers and on-chip termination, and support silicon bring-up through production ramp.

What you'll do

• Design and develop custom IO circuits, including GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces and high-speed SerDes support circuits.
• Perform transistor-level design and simulation using advanced CMOS technology nodes.
• Develop and optimize ESD protection circuits, level shifters, input buffers, output drivers and on-chip termination circuits.
• Conduct pre-layout and post-layout simulations for functionality, timing, power, noise and reliability.
• Perform signal integrity analysis, including IBIS model generation, package-aware simulations, and crosstalk and reflection analysis.
• Drive layout reviews and work closely with physical design teams to ensure design quality and performance targets.
• Support silicon bring-up, characterization, debugging and production ramp activities.
• Collaborate with system, package, reliability and product engineering teams.
• Develop and maintain design documentation, specifications and verification reports.

What you'll need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or a related field.
• 5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Strong understanding of CMOS device physics.
• Strong understanding of analog circuit design fundamentals.
• Strong understanding of IO architectures and standards.
• Strong understanding of ESD design methodologies.
• Hands-on experience in custom circuit design using Cadence Virtuoso.
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
• Good knowledge of LVS, DRC, EMIR and reliability checks.
• Familiarity with process corners, Monte Carlo analysis and yield optimization techniques.

Nice to have

• Experience with advanced technology nodes (16nm/7nm/5nm preferred).
• Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI or Ethernet interfaces.
• Knowledge of package modeling and SI/PI analysis tools.
• Understanding of ESD standards such as HBM, CDM and IEC.
• Experience in silicon validation and lab characterization.
• Scripting skills in Python, Perl, Tcl or SKILL.
• Familiarity with IBIS and IBIS-AMI model generation.
• Experience in automotive, AI/ML, networking, mobile or data center SoCs.
• Exposure to functional safety and reliability requirements.
• Prior ownership of a complete IO IP development cycle.

Details

• Location: Bangalore.