LEC CAD Engineer

Overview

LEC CAD Engineer focused on Logical Equivalence Checking (LEC) to support formal verification and silicon-ready SoC designs.

What you'll do

• Own end-to-end LEC flows across RTL-to-initmap, RTL-to-initopt, RTL-to-finalopt, gate-to-gate, and ECO verification runs.
• Debug and resolve non-equivalences, aborts, unmapped points, and incomplete verifications in complex SoC subsystems.
• Develop and maintain LEC scripts, dofiles, and automation infrastructure using Tcl, Perl, Python, or Shell.
• Integrate LEC into synthesis flows using Cadence Genus write_do_lec and Synopsys DC write_formality_script interfaces.
• Support power-aware formal verification using UPF/CPF-based flows with Conformal Low Power and Synopsys Formality.
• Triage LEC-related JIRA tickets and provide technical guidance to junior engineers; mentor on LEC methodology and debug best practices.

What you'll need

• 1+ years of hands-on ASIC/SoC CAD engineering focused on formal verification and LEC.
• Deep expertise in Cadence Conformal LEC (RTL-to-gate, gate-to-gate, ECO verification).
• Strong hands-on experience with Synopsys Formality.
• Proficiency debugging NEQs, aborts, and unmapped key points in complex hierarchical designs.
• Experience with power-aware LEC / Conformal Low Power using UPF/CPF.
• Scripting skills in Tcl, Perl, Python, and/or Shell (Bash/CSH).
• Familiarity with ASIC design flows from RTL synthesis through GDS and ECO flows.

Details

• Location: Bangalore, India.