Order Tile TestBench Design Verification Engineer

Overview

Define and execute verification plans for CPU sub-systems and build UVM-based testbenches for a SiFive order tile test bench in Hyderabad, India.

What you'll do

• Define and execute comprehensive verification plans for CPU sub-systems (e.g., Load/Store units, Memory Management Units, or Execution Pipelines).
• Build and maintain advanced, scalable verification environments using UVM (Universal Verification Methodology) and SystemVerilog.
• Develop constrained-random stimulus, directed tests, and assembly-level tests to achieve rigorous coverage targets.
• Lead complex debugging efforts at the unit and SOC levels, identifying architectural and RTL bugs.
• Provide technical leadership and guidance to junior verification engineers, ensuring best practices in coding and verification logic.

What you'll need

• 6+ years of experience in ASIC/SOC verification, specifically focused on CPU or complex IP blocks.
• Knowledge of SystemVerilog and UVM.
• Strong understanding of Computer Architecture (pipelines, caches, out-of-order execution, and memory consistency models).
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Experience with the RISC-V or ARM/x86 ISA and CPU verification experience.

Details

• Location: Hyderabad, India.
• Requires a successful background and reference checks and satisfactory proof of right to work in India.
• Offer is contingent on verifying authorization for access to export-controlled technology under applicable export control laws, or the company's ability to obtain any necessary export license(s) or other approvals.