NXP Semiconductors logo

PDK Deck Developer

NXP Semiconductors
NewPosted today

LOCATION

Noida · Onsite

EXPERIENCE

15+ Years

TYPE

FullTime

SKILLS REQUIRED

Physical VerificationDesign Rule CheckingLayout Versus SchematicParasitic ExtractionCalibrePython

Job description

Overview

Lead and manage the Process Design Kit (PDK) Physical Verification (PV) team, owning PDK PV planning, release documentation, testing, customer support and tool evaluation.

What you'll do

  • Manage and lead the PDK Physical Verification team.
  • Create Sciforma plans, PDK planning and release documents as per BCaM7 way of working.
  • Drive PDK PV testing, customer support and tool evaluations.
  • Develop PDK PV methods and procedures for continuous quality improvement, and refine PDK PV specifications and planning.
  • Continuously drive PDK PV productivity enhancements and efficiency alignment across technologies using the latest AI tools and techniques.
  • Work with cross-geographic teams to align on way of working and PDK PV release planning.
  • Develop Calibre physical verification decks for CMOS, FinFET, bulk, SOI, RF, BiCMOS and PowerMOS technologies, including DRC, LVS, PERC, Fill, LPE, and shape generation decks and scripts.
  • Develop and validate PV tools and flows using LLM-based AI tools and recent EDA AI tools such as Calibre AI and Virtuoso AI.
  • Develop the PDK infrastructure for PV tools, flows and utilities, including setups, configurations and integration of technology-specific data.
  • Perform testing, validation, customer support and new tool/method evaluations.
  • Develop methods and procedures for quality improvement, and automate deck/techFile generation and validation.

What you'll need

  • Required experience of 15+ years with PDK Physical Verification rule deck development/support and/or support of (1) physical verification rule decks/runsets (DRC/LVS/ERC/PERC/FILL) or (2) parasitic and EMIR rule decks.
  • In-depth knowledge of foundry-based and EDA tool-based process variation formats, e.g. ICT, IRCX, and understanding of the latest EMIR and EM challenges.
  • Experience with either Calibre SVRF/TVF rule deck coding or Cadence PVS/Assura rule deck coding (must have).
  • Experience with the following tools: Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk.
  • BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering or another similar discipline, with at least 15+ years of relevant experience.

Nice to have

  • Experience with at least 2 of the following programming languages: Perl, Python, SKILL, shell, C/C++, Tcl.

Read the full description and apply on the company’s own careers page.

Stay safe

Hiring on Abekus is free for applicants

We never charge a fee, and employers are prohibited from doing so. If a recruiter asks for payment, please report them right away.

PDK Deck Developer