PDN Engineer

Overview

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, focusing on power integrity sign-off (EMIR) for full-chip, block-level, die plus interposer, and chip-package-system analysis.

What you'll do

• Own full-chip and block-level static/dynamic IR drop and signal/power electromigration sign-off.
• Own die plus interposer analysis and die plus interposer plus package analysis.
• Drive root-cause debugging for voltage and EM violations and collaborate with physical design (PD) teams on floorplanning and power grid fixes.
• Own power estimation and signoff on Primepower and Joules across different use cases.
• Generate CPM on different use cases.
• Understand mixed signal IP requirements and derive metrics for signoff.
• Define and maintain robust EMIR methodologies using standard EDA tools such as Ansys RedHawk-SC or Cadence Voltus.
• Enhance flows and methods for faster convergence and cover critical gaps with changing signoff trends.
• Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams.
• Work closely with PnR on fixes for EMIR violations and on left-shift strategies for correct-by-construction methods.
• Work with DFT teams to understand the impact of DFT strategy on EMIR, assess and fix IR impact from DFT patterns, provide guidelines for toggling activity in DFT modes, and provide power estimation to ATE and board testing teams.
• Work proactively with EDA vendors to resolve tool issues, track critical issues impacting the project, and initiate and track long-term topics.
• Work with flow teams to integrate new methods and fixes into the flow that impact ongoing projects, and initiate workflows for long-term interests.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• 5+ years of relevant semiconductor industry experience, with a proven background in power integrity sign-off.
• Advanced expertise in RedHawk_SC, Voltus, and PTPX.
• Strong scripting proficiency in Python/TCL.
• Deep knowledge of the EMIR domain.
• Good knowledge of adjacent domains such as STA and inter-operation with those domains.
• Bachelor's or Master's degree in Electrical Engineering, VLSI, or a related electronics discipline.

Details

• Location: Bangalore, India.
• Job area: Engineering Group > Hardware Engineering.