PD Engineer

Overview

PD Engineer responsible for physical design implementation, timing signoff, and related semiconductor design activities for high-speed cores and ICs.

What you'll do

• Implement designs from RTL to GDSII.
• Perform physical design and timing signoff for high-speed cores.
• Lead block-level or chip-level physical design, STA, and PDN activities.
• Drive physical-design convergence against PPA targets.
• Validate constraints and resolve verification, STA, and physical-design issues.
• Handle technical deliveries with a small engineering team.

What you'll need

• At least 2 years of physical design and timing-signoff experience for high-speed cores.
• Bachelor's or master's degree in Electrical/Electronics Engineering or a related engineering field.
• At least 7 years of IC design experience.
• Experience with PDN methodology and high-frequency physical-design convergence.
• Knowledge of low-power flows, including power gating and multi-Vt flows.
• Knowledge of deep-submicron issues including leakage power, signal integrity, and DFM.
• Proficiency in Tcl or Perl scripting.

Details

• Location: Bangalore, India.