Principal Design Verification Engineer

Overview

Principal Design Verification Engineer focused on functional verification for complex SoC/silicon designs, including PCIe and CXL.

What you'll do

• Develop and execute block-level and system-level verification plans.
• Write and execute test sequences and close coverage.
• Collaborate with RTL designers to debug failures and refine verification processes.
• Write assertions and cover properties; analyze coverage data.
• Develop user-controlled random constraints in transaction-based verification.
• Create VIP abstraction layers for sequences to scale verification deployments.

What you'll need

• Minimum 12 years’ experience supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
• Bachelor’s degree required in Electrical Engineering or Computer Engineering; master’s preferred.
• Ability to interpret PCIe/CXL protocol specifications to develop and execute verification plans in simulation.
• Experience using third-party PCIe/CXL Verification IPs, focusing on Gen3 or above.
• Experience independently developing test plans and sequences in UVM to generate stimuli.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.

Nice to have

• Expertise verifying Physical/Link/Transaction layers of PCIe/CXL including compliance on PCIe/CXL EP/RC.
• Experience with buffering and queuing with QoS on complex NOC-based SoCs.
• Experience analyzing system-level performance on switching fabrics.

Details

• Location: Bengaluru, Karnataka, India.