Principal Engineer, Asic Design

Overview

Principal Engineer, ASIC Design to drive IP, Subsystem, and SoC development for next-generation memory and storage products, with hands-on expertise in micro-architecture, RTL design, and end-to-end SoC execution, and close collaboration across global teams.

What you'll do

• Own end-to-end IP and SoC development from micro-architecture through RTL design, integration, and physical hardware assistance.
• Own IP and Subsystem design from scratch, ensuring high-quality, reusable RTL.
• Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis.
• Define and review module interfaces and system-level architecture.
• Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams.
• Support post-silicon debug and bring-up activities.
• Provide technical mentorship and participate in design and methodology reviews.
• Use Micron-approved AI tools and AI-enabled workflows to improve engineering productivity, design quality, automation, and decision-making across the SoC development lifecycle, in compliance with Micron AI governance standards.

What you'll need

• 12+ years of hands-on IP and SoC RTL design experience.
• Strong expertise in micro-architecture, Verilog/SystemVerilog, and RTL integration.
• Solid knowledge of asynchronous design concepts and CDC methodologies.
• Deep understanding of SoC design flows (Lint, CDC, Synthesis/STA, Power).
• Strong fundamentals in digital design and scripting languages.
• Excellent problem-solving and communication skills.
• Ability to work effectively with global multi-functional teams.

Nice to have

• Exposure to LPDDR Subsystem, CPU Subsystems, and SoC Test Controller design.
• Experience with ASIC controllers for storage or memory systems.
• Hands-on post-silicon debug and silicon support experience.

Details

• Location: Hyderabad - Phoenix Aquila, India.