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Principal Engineer, ASIC Validation

Micron Technology
NewPosted today

LOCATION

Hyderabad · Onsite

EXPERIENCE

12+ Years

TYPE

FullTime

SKILLS REQUIRED

Hardware ArchitectureVerilogRoot Cause AnalysisDebuggingPythonPerlSignal IntegrityTest Automation

Job description

Overview

Principal Engineer role focused on ASIC validation, owning SoC deployment on pre-silicon emulation platforms and driving PCIe, LPDDR and ONFI subsystem validation with design, firmware and architecture teams.

What you'll do

  • Hold overall ownership of complete SoC deployment on pre-silicon platforms on ZEBU.
  • Work with Design/SoC C/FW teams to identify actual firmware implementation and plan and perform validation accordingly.
  • Review the SoC verification plan for the PCIe/LPDDR/ONFI subsystems and create or understand PCIe/LPDDR/ONFI validation plans with SoC C, AE and FW teams.
  • Develop understanding of the SoC and perform processor-based SoC prototyping and emulation using C/FW/AE flow.
  • Run SoC C-based simulations for test case understanding and debug using VCS.
  • Work with overseas teams for PCIe/LP bring-up and debug.
  • Write Verilog RTL when required and debug using Xilinx FPGA Vivado flow.

What you'll need

  • Bachelor's or Master's degree or equivalent experience in Engineering.
  • Hands-on Xilinx FPGA flow, Vivado flow and protocompiler tool flow or ZEBU emulation flow.
  • Hands-on ZEBU experience.
  • Minimum 12+ years of processor-based SoC and hands-on ZEBU implementation experience.
  • Proficiency in FPGA debug skills, with practical experience in Xilinx FPGA debug using Chipscope flow.
  • Strong root-cause skills across hardware and RTL layers.
  • Good understanding of any of PCIe/NVME/LPDDR/ONFI architecture.
  • Strong Verilog coding skills.
  • Proven experience in scripting languages such as Python, Perl or TCL.
  • Good written and oral communication.
  • Positive attitude, well-mannered and mature behaviour.

Nice to have

  • Hands-on HAPS 100, HAPS 200, ZEBU and Palladium experience (most preferred).
  • Thorough knowledge of ZEBU or Palladium flow, Xilinx UltraScale FPGA and Vivado flow.
  • Leverage AI-enabled tools to improve productivity and decision making.
  • Knowledge of industry-standard interfaces such as ONFI, AXI, LPDDR and PCIe.

Details

  • Location: Hyderabad - Phoenix Aquila, India.

Read the full description and apply on the company’s own careers page.

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Principal Engineer, ASIC Validation