Principal Engineer – Design Verification

Overview

Principal DV Engineer to anchor the verification of next-generation, high-performance networking silicon, acting as the primary technical driver for complex IPs and critical sub-systems.

What you'll do

• Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.
• Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.
• Author comprehensive verification plans; drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).
• Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.
• Actively participate in design and verification code reviews, maintaining high standards of code quality, reuse, and documentation within the execution team.
• Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.

What you'll need

• 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.
• Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.
• Mastery of System Verilog and UVM, with a proven history of writing complex testbenches and VIP integrations from scratch.
• Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.
• B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Hands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.
• Proficiency in Python or Perl for testbench automation and triage scripting.

Details

• Location: Bangalore, India.