Principal Engineer

Overview

Principal Engineer role focused on post-silicon physical layer electrical validation and characterization of high-speed SerDes devices.

What you'll do

• Perform post-silicon device validation and debugging of high-speed SerDes.
• Lead laboratory testing of test chips to validate high-speed physical layer electrical performance.
• Run compliance testing for interfaces including PCIe, USB, Ethernet, and DDR.
• Develop and maintain hardware infrastructure and automation scripts for test characterization.
• Analyze, debug, and root-cause silicon issues using oscilloscopes, network analyzers, and BERT.
• Create test plans, characterization reports, and related documentation.
• Collaborate with design and product engineering teams on post-silicon findings.

What you'll need

• B.E/B.Tech or M.E/M.Tech in Electrical/Electronics Engineering.
• 8–10 years (BTech) or 6–8 years (MTech) experience in post-silicon physical layer electrical validation.
• Deep knowledge of high-speed SerDes protocols including PCIe, USB, CXL, and Ethernet.
• Good understanding of jitter decomposition, equalization, and de-embedding techniques.
• Hands-on experience with high-bandwidth oscilloscopes, BERT, and VNA.
• Proficiency in Python and Linux for test automation.

Details

• Location: India - Bangalore.
• Travel time: 0% - 25%.