Principal SOC Physical Verification & Integration Specialist

Overview

Principal SOC Physical Verification & Integration Specialist to lead physical assembly and signoff of next-generation SOCs from floorplan through tapeout.

What you'll do

• Drive full-chip physical assembly, including top-level floorplanning, bump planning, and global power grid integration.
• Architect hierarchical physical verification flows with defined boundary conditions, abstraction models, and interface rules.
• Own full-chip signoff and execute debugging for DRC, LVS, ERC, Antenna, ESD, and Latch-up at advanced nodes.
• Collaborate with Physical Design (PD) and Static Timing Analysis (STA) teams to resolve integration conflicts.
• Co-optimize design rules with foundry partners to interpret rules and handle edge-case violations for reticle-limit designs.
• Develop scripts and utilities for automating integration tasks, database merging, and PV result parsing.

What you'll need

• 14+ years of hands-on experience in SOC physical design and physical verification, including taping out very large complex SOCs.
• Deep understanding of the RTL-to-GDSII flow and physical integration challenges in flat vs hierarchical methodologies.
• Foundational understanding of Physical Design and Static Timing Analysis (STA).
• Mastery of top-level integration tools such as Cadence Innovus.
• Expertise with physical verification suites (e.g., Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator).
• High proficiency in Tcl, Python, and/or Perl for EDA flow automation and database manipulation.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Details

• Location: Bangalore (Hybrid), India (Remote).
• Work mode: Hybrid/Remote (as stated in the ATS line).