Sr. Memory Layout Design Engineer

Overview

Sr. Memory Layout Design Engineer responsible for end-to-end memory layout deliverables, quality, and schedule.

What you'll do

• Apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Own start-to-end deliverables and meet planned schedule with quality.
• Communicate and coordinate with the SOC/library team on new methodologies.
• Support layout scripting and automation.

What you'll need

• Minimum 8 years of experience with strong layout knowledge.
• Bachelor's degree required.
• Proficiency with Cadence tools including Virtuoso layout, layout XL, schematic capture, and verification tools.
• Experience in submicron processes such as 7nm, 5nm, 3nm, or 2nm.
• Experience in digital layout including Standard cell, Memory, and I/O.
• Memory layout design and physical verification experience (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.

Nice to have

• Analog layout experience is a plus.
• Experience with memory compilers is a plus.

Details

• Location: IND-Bangalore Electronic City - S1.