CPU Integration/Physical Verification CAD engineer (Lead/Staff/Sr Staff)

Overview

CPU Integration/Physical Verification CAD engineer focused on floor-planning, physical design, physical design verification, and signoff for Qualcomm Oryon CPU cores.

What you'll do

• Enable floor-planning for Oryon CPU cores.
• Support physical design (PD) activities.
• Perform physical design verification (PDV) and signoff.
• Manage and regress place-and-route flows.
• Work on place-and-route, analysis, timing sign-off, and PDV tasks.
• Develop and optimize CAD verification/test related processes and automation.

What you'll need

• 6+ years of hardware engineering experience (or 5+ with a Master’s, or 4+ with a PhD).
• Hands-on experience in development of high-performance chips in a design or CAD role for 6+ years.
• Programming proficiency in Python and Tcl.
• Knowledge of data structures and algorithms.
• Experience with automation.
• Strong experience with physical design tasks including place-and-route, timing sign-off, and PDV.

Details

• Location listed as Bangalore, India and Noida, Uttar Pradesh, India.