Director, Physical Design

Overview

Director, Physical Design to lead and grow Astera Labs’ physical design function in Hyderabad.

What you'll do

• Build and mentor a physical design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology.
• Own end-to-end physical implementation from floor planning through GDSII signoff for complex SoCs/ASICs.
• Drive placement, CTS, routing, timing closure, power analysis, and physical verification (DRC/LVS).
• Oversee timing closure across multiple corners/modes (MMMC) for robust STA signoff at advanced nodes.
• Establish and continuously improve PD flows, methodologies, checklists, and best practices.
• Evaluate and deploy EDA tools and drive automation using scripting (Tcl/Python/Perl).

What you'll need

• 18+ years of experience in ASIC physical design.
• At least 5 years in a leadership or management role.
• Hands-on experience with full-chip physical design (floorplanning, PnR, CTS, STA, IR/EM analysis, physical verification).
• Proficiency with tools including Cadence Innovus, Synopsys Fusion Compiler/IC Compiler, PrimeTime, Calibre, and RedHawk/Voltus.
• Proven track record of multiple successful tapeouts at advanced nodes (7nm or below).
• Scripting skills in Tcl, Python, or Perl.

Details

• Location: Hyderabad, Telangana, India.