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Senior ASIC Validation Engineer

Qualcomm
NewPosted yesterday

LOCATION

Bangalore · Onsite

EXPERIENCE

2+ Years

SKILLS REQUIRED

Post-Silicon ValidationFirmware DevelopmentRoot Cause AnalysisC ProgrammingDebugging

Job description

Overview

Senior ASIC Validation Engineer role at Qualcomm India Private Limited in the ASICS Engineering group, focused on low-level firmware, post-silicon bring-up and validation of ASIC/SoC products.

What you'll do

  • Develop low-level drivers, bootloaders, BSPs, middleware, and application firmware.
  • Work closely with hardware, RTL and DV engineers to develop and debug.
  • Lead post-silicon bring-up and validation of a given module of ASIC/SoC products.
  • Drive debug and root-cause analysis of silicon, firmware, and system-level issues.
  • Develop firmware and low-level software required for silicon bring-up, subsystem enablement, and debug.
  • Debug complex hardware-software integration issues using oscilloscopes, logic analyzers, protocol analyzers, JTAG/SWD debuggers, and other laboratory equipment.
  • Analyze protocol traces, link training behavior, LTSSM states, error logs, and performance bottlenecks.
  • Develop production-quality software, including testing, documentation, static analysis, and CI/CD/CT.
  • Develop Python-based automation frameworks for validation and regression testing.
  • Interact with hardware, software and other teams to validate SoCs with minimum delays.

What you'll need

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field.
  • Strong programming skills in C and C++ for resource-constrained systems.
  • Proficient in Python programming.
  • Excellent knowledge in low-level firmware/bare-metal HW/IP driver writing.
  • Root-cause analysis of silicon failures and hardware debug and failure isolation.
  • Performance characterization and power and thermal validation.
  • In-depth understanding of the HW is a must.
  • Exposure to hardware initialization, validation diagnostics development and firmware optimisations.
  • Good knowledge of how to use embedded development tools such as JTAG and associated debug tools.
  • Work experience on ARM Cortex platform/MIPS/RISC-V CPUs.
  • Good knowledge of system software stack, power management, high-speed peripherals, USB, SDIO, Ethernet, PCIe, and memory subsystems like DDR/LPDDR.
  • Exposure to PCIe Gen4/Gen5/Gen6, 25G/50G/100G/200G/400G Ethernet, CXL, DDR4/DDR5/LPDDR, SerDes, UCIe interface validation.
  • Familiarity with software configuration management tools, defect tracking tools, and peer review.
  • Work experience on heterogeneous and multiprocessor SoC platforms.
  • Experience with development environments such as Linux, Git, Jira and Confluence.
  • Strong communication skills to exchange ideas and work as a team.

Nice to have

  • Work experience with FPGA-based platforms.
  • Exposure to pre-silicon environment with RTL co-simulations.

Details

  • Location: Bangalore, India.

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Senior ASIC Validation Engineer