Senior CAD Engineer – Physical Design Signoff

Overview

Develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs, working with Physical Design, Timing, Power, Reliability and CAD teams to improve signoff quality, productivity and turnaround time.

What you'll do

• Develop and enhance automation solutions for Physical Design signoff flows, including RC Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), Power Integrity (IR Drop/EM) and Signal Integrity (SI).
• Create scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity.
• Develop scripts and tools to automate signoff checks, debugging, reporting and data analysis.
• Analyze and resolve timing, extraction, ERC and power signoff issues in collaboration with design teams.
• Drive methodology improvements to improve signoff convergence, quality and correlation across implementation stages.
• Partner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities.
• Build dashboards and reporting infrastructure to monitor signoff health and project readiness.

What you'll need

• M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field.
• 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation.
• Strong proficiency in Python.
• Strong proficiency in Tcl Shell scripting.
• Deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC) and Power Integrity signoff.

Nice to have

• Experience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent).
• Understanding of AOCV/POCV and variation-aware timing methodologies.
• Familiarity with power delivery networks, EM analysis and reliability signoff.
• Experience in Machine-learning methods and Agentic AI systems to solve CAD problems.
• Exposure to CPU core, high-performance compute or large SoC designs.
• Experience with distributed computing environments and large-scale signoff infrastructure.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.