Senior Design For Test Engineer

Overview

Senior Design For Test (DFT) Engineer responsible for implementing DFT and test on complex IP and SOC for ASIC designs, performing DFT insertion and/or verification tasks for the team.

What you'll do

• Perform DFT insertion and/or verification tasks for complex IP and SOC ASIC designs.

What you'll need

• Strong fundamentals in digital circuit design.
• Scripting skills using PERL, Tcl and C-Shell.

Nice to have

• Experience with Cadence/Mentor/Synopsys tool set (Genus, Modus and NCSim / Tessent / Spyglass).

Details

• Location: Bangalore.
• Eligible for Marvell bonus and equity plans, including a new hire equity grant and annual equity refreshers.
• Candidates may be subject to an export license review process; applicants must be eligible to access export-controlled information under applicable law.
• Candidates must not use AI tools during interviews; use without prior instruction from the interviewer results in disqualification.