Senior Design Verification Engineer

Overview

Senior Design Verification Engineer to develop and deliver verification for next-generation DRAM and emerging memory technologies.

What you'll do

• Develop and complete verification plans, testcases, regressions, and coverage strategies for complex memory builds.
• Build and improve verification environments using SystemVerilog, UVM, and industry-standard verification methodologies.
• Debug build and verification issues and perform root-cause analysis for functional and timing defects.
• Develop scripting and automation solutions to improve verification efficiency, productivity, and quality.
• Collaborate with global and cross-functional teams to define verification strategies for product development.

What you'll need

• Bachelor’s or master’s degree in electrical engineering, electronics engineering, computer engineering, or related field, or equivalent experience.
• Strong understanding of semiconductor fundamentals, digital build, and CMOS circuits.
• Experience with SystemVerilog, UVM, and verification methodologies for digital and/or mixed-signal builds.
• Familiarity with simulation and verification tools including Xcelium, Verilog, SpectreFX, or comparable tools.
• Strong debugging, analytical, problem-solving, and communication skills.

Nice to have

• Experience developing automation tools and scripts using Python, Perl, or similar languages.
• Familiarity with verification metrics, completeness-focused verification approaches, assertions (SVA), and verification signoff.
• Experience with Cadence and/or Synopsys build and verification tools.
• Knowledge of DRAM, memory products, or semiconductor verification flows.
• Experience using AI-assisted engineering tools to improve verification efficiency and problem-solving.