Senior DRAM Systems Architecture

Overview

Provide systems-level architecture leadership for next-generation memory solutions, combining analytical modeling, architecture development, reliability strategy, and cross-functional influence to help define future products.

What you'll do

• Define architectures for DDR, LPDDR, HBM, CXL-attached memory, and emerging memory technologies.
• Develop analytical and simulation-based models to evaluate performance, reliability, power, thermal, and cost tradeoffs.
• Drive architecture requirements across DRAM, packaging, modules, controllers, platforms, and system software.
• Lead technical studies, roadmap development, and architecture recommendations supported by quantitative analysis.
• Influence cross-functional teams, mentor engineers, and contribute to patents, publications, and standards activities.

What you'll need

• Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, Applied Mathematics, Physics, or a related technical field.
• 8+ years of experience in memory systems, semiconductor architecture, computer architecture, or related technical areas.
• Strong knowledge of DRAM architecture, memory systems, or high-performance computing system architecture.
• Proven ability to develop architecture recommendations using quantitative analysis and engineering tradeoffs.
• Experience using AI-powered tools and methodologies, including Large Language Models, Agentic AI, Generative AI, or AI-enabled simulation environments.

Nice to have

• Experience working with DDR, LPDDR, HBM, CXL memory, MRDIMM/RDIMM, or emerging memory technologies.
• Experience with memory-system simulation or modeling tools such as Ramulator, Ramulator2, DRAMsim3, gem5, internal simulators, or equivalent platforms.
• Experience in queueing theory, stochastic modeling, performance modeling, reliability modeling, or mathematical optimization.
• Experience with RAS architecture, ECC, CRC, EDC, metadata, on-die ECC, rank-level protection, link protection, or system-wide robustness.
• Background in high-speed signaling, SI, clock distribution, packaging, module, PMIC, power, or thermal systems and experience participating in JEDEC or similar standards organizations.

Details

• Technical Staff Member role.
• Location: Bengaluru, Karnataka, India.