Senior Engineer (Level 2)

Overview

Senior Engineer responsible for functional verification of SOC, IP, or block-level designs using SystemVerilog and UVM.

What you'll do

• Develop test plans and UVM testbench components.
• Build verification environments and interface agents.
• Develop UVM scoreboards.
• Debug RTL, testbench, and test-failure issues.
• Close coverage and bug reports for verification closure.
• Develop and maintain scripts.
• Adapt to runtime changes in schedules and designs.

What you'll need

• 4+ years of experience in SOC, IP, or block-level functional verification.
• Experience with SystemVerilog and UVM.
• Strong knowledge of advanced UVM.
• Knowledge of at least one protocol such as Ethernet, PCIe, MIPI, USB, or AMBA.
• Understanding of the complete functional verification cycle.

Details

• Location: Bangalore, India.
• Employment type: Full time.