Senior High Speed IO Validation Engineer

Overview

Own end-to-end characterization and validation of high-speed IO interconnects on new NVIDIA GPU, CPU and SoC silicon, from die through package and board, for datacenter, AI and client markets.

What you'll do

• Own end-to-end characterization and validation of high-speed IO (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from silicon die through package and board, on NVIDIA GPUs, CPUs and SoCs.
• Develop and execute validation test plans for silicon and SoC-level HSIO features, including bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal and firmware variables.
• Drive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level), analyze trade-offs across V/F, lane config and protocol state, and feed results back into design, firmware and binning.
• Drive systematic root-cause analysis for complex HSIO bugs across silicon, package, board, firmware and driver, with platform, thermal and mechanical partners when system context matters.
• Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream.
• Assess manufacturing and yield implications of HSIO margin distributions, identify gaps in scaling from chip to product, and feed back into binning and design.
• Develop and improve validation methodologies, automation frameworks and margin-tracking infrastructure as platform complexity grows.

What you'll need

• BS or MS in Electrical or Computer Engineering (or equivalent).
• 6+ years in post-silicon HSIO validation, characterization, or a closely related discipline.
• Deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and the underlying SERDES architecture, including equalization, link training and electrical characterization, with strong signal integrity and jitter knowledge.
• Strong SI and PI fundamentals: S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition.
• Validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.
• Hands-on with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR), DOE/shmoo/margin trending, and Python-based test automation.
• Track record of driving cross-functional debug across chip, package, board, firmware, driver and system teams.

Nice to have

• Hands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon, including link training, equalization tuning, BER margining or compliance debug.
• Prior SERDES, mixed-signal or analog circuit design experience, sufficient to form hypotheses, design Sim-to-Si correlation experiments and propose silicon/system-side fixes during debug.
• Track record of translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization, finding marginality at die-and-board scale before it appears in the field.
• Comfortable using AI productivity tools (Claude, Copilot or equivalent) to compress log triage, regression analysis, scripting and reporting workflows.

Details

• Location: Bengaluru, India.
• Work mode: Hybrid.