FPGA Silicon Validation Engineer

Overview

Own FPGA post-silicon validation for assigned domains and products, leading design bring-up, PVT and non-PVT testing including regression, and driving debug to closure.

What you'll do

• Lead design bring-up on FPGA/silicon, owning validation covering PVT (corners, voltage/temperature sweeps, fmax/margin, stress) and non-PVT (functional, feature, system) testing.
• Define, maintain, and scale regression suites (content, automation, overnight runs, fail triage, exit criteria).
• Architect and deliver design/test automation in Python, Tcl, and C.
• Use RTL and on-chip debug to root-cause failures across hardware, timing, firmware, and board.
• Set test plans, coverage expectations, and validation exit criteria for assigned work.
• Define and deliver continuous improvement of the silicon validation environment and methodologies.
• Debug and resolve silicon bring-up issues, document solutions, and troubleshoot and debug silicon from prototype to production.
• Partner with DV, IPSS, and Customer Support on correlation, integration, and customer/field issues.
• Mentor junior engineers, reviewing bring-up quality, regression health, and documentation.
• Represent validation in milestone reviews and technical escalations.

What you'll need

• B.E. / B.Tech / M.S. in ECE, EE, Computer Engineering, or related field.
• 5–8 years of experience in post-silicon / FPGA / HW validation or protocol bring-up, aligned to Grade 6 / 7.
• Proven ownership of design bring-up and HW validation through production-quality outcomes.
• Hands-on PVT and regression planning, execution, and fail analysis.
• Strong HW knowledge plus automation in Python, Tcl, and C.
• Solid RTL debug ability (Verilog/SystemVerilog or VHDL).
• FPGA tool and lab proficiency (JTAG/debug, scopes/analyzers, protocol tools as applicable).
• Demonstrated collaboration with DV, IP/integration (IPSS or equivalent), and customer-facing teams.
• Clear technical writing for plans, bugs, and status.

Nice to have

• Depth in one or more of: Ethernet, ANLT, PTP, D-PHY, CPRI, JESD, SerialLite, DP, HDMI, SATA, SAS.
• Thermal chamber / shmoo / margin characterization.
• Board/schematic literacy; basic SI/PI for high-speed links.
• Mentored juniors or led a validation workstream.
• Emulation or pre-silicon to post-silicon correlation experience.

Details

• Employment type: Regular.
• Shift: Shift 1 (India).
• Primary location: Bengaluru, Karnataka, India.