Senior Lead Engineer - STA

Overview

Digital Physical Design Engineer responsible for full STA signoff for an SoC or subsystem through tapeout.

What you'll do

• Perform complete STA signoff for the SOC or subsystem.
• Write and refine timing constraints through the SOC design cycle.
• Interact with Frontend, DFT, and IP teams to produce correct constraints.
• Validate constraints to ensure correctness.
• Drive complete timing signoff until tapeout for subsystem or full chip.
• Lead signoff activities.
• Contribute to physical design problem solving and define physical design strategy by technology node.

What you'll need

• Have exposure to AI and use AI in STA activities.
• Have worked on SDF generation and validation.
• Have knowledge of SI closure.
• Have exposure to higher technology nodes such as 16nm and 5nm.
• Be conversant with physical design flows and functions, including placement, CTS, and routing.

Details

• Location: Noida.