Senior Lead STA Engineer

Overview

Lead static timing analysis for ASIC development, focusing on timing convergence, physical implementation, power, and PPA optimization.

What you'll do

• Perform static timing analysis for ASIC designs.
• Develop constraints and support physical implementation activities.
• Fix extreme critical timing bottleneck paths.
• Prepare complex ECOs for timing convergence across multiple corners.
• Optimize power and push performance, power, and area improvements.
• Collaborate with cross-functional engineering groups on product execution.

What you'll need

• At least 3 years of relevant ASIC design, verification, validation, integration, or related experience with a bachelor's degree.
• At least 2 years of relevant experience with a master's degree.
• At least 1 year of relevant experience with a PhD.
• At least 5 years of static timing analysis, constraints, and physical implementation experience.
• Proficiency with tools including PT, Tempus, GENUS, Innovus, and ICC.
• Expertise in Perl and Tcl.
• Strong fundamentals in high-performance and low-power implementation.

Nice to have

• Experience with deep submicron process technology nodes.
• Knowledge of high-performance and low-power implementation methods.

Details

• Location: Noida, Uttar Pradesh, India.