Senior Manager ASIC Verification

Overview

Lead a team responsible for designing and verifying complex mixed-signal ICs that integrate analog and digital components, ensuring first-pass silicon success.

What you'll do

• Architect and design digital blocks for integration in CMOS ICs.
• Specify and design digital blocks at RTL level and add DfT concepts to the design.
• Perform synthesis, block verification and gate-level analysis of implemented digital blocks for on-silicon integration.
• Implement and verify ECOs on existing designs.
• Technically lead digital design tasks in strong cooperation with the project technical lead and project manager.
• Develop testbenches using SystemVerilog and UVM for functional and power-aware RTL.
• Develop UVM components such as active and passive agents, scoreboards and environments.
• Develop assertions and functional coverage.
• Develop test plans, UVM-based test sequences, layered sequences and virtual sequencers.
• Drive closure of verification metrics to cover the verification space.
• Work with the team to identify and close gaps in functional, power-aware and gate-level timing simulation.
• Manage and mentor a team of digital and digital DV engineers.
• Drive hiring, performance reviews and career development.
• Foster a culture of technical excellence and innovation.

What you'll need

• Master's or PhD in Electrical Engineering or a related field.
• 10+ years of experience in mixed-signal IC verification, with 3–5 years in a leadership role.
• Knowledge of digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting and synthesis constraining.
• Proficiency in Verilog, Verilog-A/AMS, UVM and scripting languages (Python, Perl, Tcl).

Details

• Location: Hyderabad.