Senior Memory Design Engineer

Overview

Senior Memory Design Engineer focused on DRAM memory array and related circuits, including schematic/layout, verification, and integrating AI-driven design flows.

What you'll do

• Assist with the design, layout, and optimization of DRAM memory array and peripheral logic/analog circuits.
• Use AI-based tools, agentic workflows, and automation frameworks to optimize schematics and explore design space.
• Perform parasitic analysis, sensitivity studies, and corner coverage to support design readiness.
• Improve debug efficiency across simulation and silicon learning loops.
• Oversee memory layout, including floor-planning, placement, and routing.
• Carry out circuit-level verification (functional, timing, power, reliability) using simulators and tools.
• Collaborate with CAD, EDA, and software teams to integrate AI-driven flows into simulation/verification/design sign-off environments.

What you'll need

• Master’s degree in electrical or computer engineering.
• 4-8 years of experience in memory design.
• Strong fundamentals in CMOS circuit design, device physics, and memory operation.
• Experience with SPICE-based simulation and parasitic extraction.

Nice to have

• Domain knowledge in DRAM design (DDR5, LPDDR5, HBM, or other DRAM-related fields).
• Exposure to AI/ML-assisted design flows, agentic AI, or advanced automation in circuit design and verification.
• Domain knowledge in NAND memory design.
• Experience on SoC/ASIC semicustom flow.
• Strong communication and collaboration skills.

Details

• Location: Hyderabad - Phoenix Aquila, India.