Memory Design Engineer

Overview

Memory Design Engineer responsible for designing and developing SRAM, register file compilers, and related simulation and characterization flows.

What you'll do

• Contribute/lead design and development of single/multiport SRAM and register file compilers in 28nm/16FF/7FF/5FF technologies.
• Perform circuit design and simulation for key components including bitcell, WL decoder, SAMP, column decoder, and control logic.
• Develop critical path and characterization flows for detailed margin and characterization simulations.
• Conduct statistical analysis of bit-cell, sense amplifier, and self-time blocks for compiler target yield sign-off.
• Tune designs, perform margin analysis, and sign off complete compiler for yield and performance targets.
• Run logic simulations and detailed timing analysis for key paths in high-speed memory design.
• Perform signal-integrity (EM) and power-integrity (IR drop) analysis and design.

What you'll need

• Expertise in high speed/low power CMOS circuit design, clocking schemes, and static/dynamic logic circuits.
• Experience designing and driving one or more memory compiler specifications to final release.
• Deep expertise in split-rail and power-gating architecture and circuit design.
• Hands-on experience with silicon debug/diagnose failures and fixing silicon failures.
• Hands-on experience using Cadence/Mentor schematic/layout editor tools.
• Hands-on experience with circuit simulation and MC analysis tools (e.g., HSPICE/HSIM/XA/FinSim/XARA/nWave).
• Experience in layout design issues in sub-nanometer regime.

Details

• Location: IND-Bangalore Electronic City - S1.